235 lines
5.9 KiB
C
235 lines
5.9 KiB
C
#pragma Off (List)
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/*******************************************************************************
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* FILE NAME: Flash_SK_IO.ch
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*
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* TITLE: This function prototypes and data type definitions.
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*
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* DATA_RIGHTS: Western Design Center and R & C Services Proprietary
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* Copyright(C) 1980-2004
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* All rights reserved. Reproduction in any manner,
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* in whole or in part, is strictly prohibited without
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* the prior written approval of R & C Services or
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* Western Design Center.
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*
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* DESCRIPTION: This file describes function prototypes and data type
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* definitions used for .
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*
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*
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* SPECIAL CONSIDERATIONS:
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* <None>
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*
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* AUTHOR: R. Greenthal
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*
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*
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* CREATION DATE: Feb 05,2004
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*
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* REVISION HISTORY
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* Name Date Description
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* ------------ ---------- ----------------------------------------------
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* R. Greenthal 02/05/2004 Initial
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*
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*******************************************************************************
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*/
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#ifndef Flash_SK_IO_H
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#define Flash_SK_IO_H
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/*
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*=========================== CONSTANTS & MACROS ===============================
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*/
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/* None */
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/*
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*================================== TYPES =====================================
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*/
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/* None */
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/*
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*============================= FUNCTION PROTOTYPES ============================
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*/
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#define CLI asm{cli;} /* enable interrupt response */
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#define SEI asm{sei;} /* disable it */
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#define BRK(n) asm{ brk n;} /* 65C02/65c816-BRK */
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#define COP(n) asm{ cop n;} /* 65c816-COP */
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//#define EnableIRQ(n)\
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// asm(" lda #$80\n"\
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// " tsb $fd01+"#n"*4\n") /* enable interrupt of timer n */
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//#define DisableIRQ(n)\
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// asm(" lda #$80\n"\
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// " trb $fd01+"#n"*4\n") /* disable it */
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struct _VIA1{
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uchar ORB_IRB; /* Input/Output Reg 'B' */
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uchar ORA_IRA; /* Input/Output Reg 'A' */
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uchar DDRB; /* Data Direction Reg 'B' */
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uchar DDRA; /* Data Direction Reg 'A' */
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uchar T1CLO; /* Timer #1 Counter Low */
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uchar T1CHI; /* Timer #1 Counter High */
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uchar T1LLO; /* Timer #1 Latch Low */
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uchar T1LHI; /* Timer #1 Latch High */
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uchar T2CLO; /* Timer #2 Counter Low */
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uchar T2CHI; /* Timer #2 Counter High */
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uchar SR; /* Shift Reg */
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uchar ACR; /* Auxiliary Control Reg */
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uchar PCR; /* Peripheral Control Reg */
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uchar IFR; /* Interrupt Flag Reg */
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uchar IER; /* Interrupt Enable Reg */
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uchar ORANH_IRANH; /* Input Reg 'A' No Handshake */
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};
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struct _VIA2{
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uchar ORB_IRB; /* Input/Output Reg 'B' */
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uchar ORA_IRA; /* Input/Output Reg 'A' */
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uchar DDRB; /* Data Direction Reg 'B' */
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uchar DDRA; /* Data Direction Reg 'A' */
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uchar T1CLO; /* Timer #1 Counter Low */
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uchar T1CHI; /* Timer #1 Counter High */
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uchar T1LLO; /* Timer #1 Latch Low */
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uchar T1LHI; /* Timer #1 Latch High */
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uchar T2CLO; /* Timer #2 Counter Low */
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uchar T2CHI; /* Timer #2 Counter High */
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uchar SR; /* Shift Reg */
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uchar ACR; /* Auxiliary Control Reg */
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uchar PCR; /* Peripheral Control Reg */
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uchar IFR; /* Interrupt Flag Reg */
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uchar IER; /* Interrupt Enable Reg */
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uchar ORANH_IRANH; /* Input Reg 'A' No Handshake */
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};
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struct _UART16c450{
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uchar RHR_THR; /* Transmit/Receive Holding Register */
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uchar IER; /* Interrupt Enable Register */
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uchar FCR_ISR; /* FIFO control Register/Interrupt Status Register */
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uchar LCR; /* Interrupt Status Register */
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uchar MCR; /* Modem Control Register */
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uchar LSR; /* Line Status Register */
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uchar MSR; /* Modem Status Register */
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uchar SCR; /* Scratch pad Register */
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};
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#define clock 1.84320E+06
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//#define clock 3.686400e6
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//#define clock 6.144000e6
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//#define clock 7.372800e6
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//#define clock 1.4743600e7
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// UART 16c450 Type Baud Rates
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#define _COM_300_ (clock/(16 * 300))-1
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#define _COM_1200_ (clock/(16 * 1200))-1
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#define _COM_2400_ (clock/(16 * 2400))-1
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#define _COM_9600_ (clock/(16 * 9600))-1
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#define _COM_19K_ (clock/(16 * 19200))-1
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#define _COM_38K_ (clock/(16 * 38400))-1
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#define _COM_56K_ (clock/(16 * 57600))-1
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#define _COM_115K_ (clock/(16 * 115200))-1
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//* Parity
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#define _COM_NOPARITY_ 0
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#define _COM_ODDPARITY_ 1
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#define _COM_EVENPARITY_ 2
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//* Stopbits
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#define _COM_STOP1_ 0
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#define _COM_STOP2_ 1
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#define _COM_STOP1_5_ 1
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//* word length
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#define _COM_CHR5_ 0
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#define _COM_CHR6_ 1
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#define _COM_CHR7_ 2
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#define _COM_CHR8_ 3
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//* word Buffer length
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#define _COM_FIFO1_ 0
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#define _COM_FIFO4_ 1
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#define _COM_FIFO8_ 2
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#define _COM_FIFO14_ 3
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struct _UART51{
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uchar rxd_txd; /* Receiver register */
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uchar serial_status; /* xmit & receive status reg */
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uchar serial_command; /* command register */
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uchar serial_control; /* rate & size control */
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};
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#define RXD_READY 0x08 /* receiver ready bit mask */
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#define TXD_READY 0x10 /* transmitter ready bit mask */
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#define RXD_INT_ENABLE 0x02 /* receiver interrupt enable bit mask */
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#define TXD_INT_ENABLE 0x04 /* transmitter interrupt enable bit mask */
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#define RXD_ERROR 0x07 /* frame, overrun & parity error flags */
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#define clock51 1.84320E+06
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//#define clock51 3.686400e6
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//#define clock51 6.144000e6
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//#define clock51 7.372800e6
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//#define clock51 1.4743600e7
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// UART W65c51 Type Baud Rates
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#define _COM51_300_ (clock51/(16 * 300))
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#define _COM51_1200_ (clock51/(16 * 1200))
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#define _COM51_2400_ (clock51/(16 * 2400))
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#define _COM51_9600_ (clock51/(16 * 9600))
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#define _COM51_19K_ (clock51/(16 * 19200))
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#define _COM51_38K_ (clock51/(16 * 38400))
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#define _COM51_56K_ (clock51/(16 * 57600))
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#define _COM51_115K_ (clock51/(16 * 115200))
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struct _134_TOD_Clock{
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uchar tenthsec;
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uchar sec;
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uchar min;
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uchar hr;
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uchar day;
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uchar month;
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uchar yr;
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uchar daywk:3;
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uchar nu1:5;
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uchar daylit:1;
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uchar nu2:7;
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};
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struct _Maxim_TOD_Clock{
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uchar sec;
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uchar min;
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uchar hr;
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uchar day;
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uchar month;
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uchar yr;
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};
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struct _I2C{ /* One byte of the VIA */
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uchar clock:1;
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uchar sin:1;
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uchar sout:1;
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uchar nu:5;
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};
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#endif /* Flash_SK_IO_H */
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#pragma Pop (List)
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